The development of nonvolatile memories based on the principle of trapping electrical charge in an isolated gate (floating) of a field effect transistor (cell) to modify its turn-on threshold, has had and continues to have an extremely important role in the achievement of ever increasing levels of compactness, speed and low consumption of integrated systems. The development of such memories is strictly tied to a parallel development of suitable fabrication technologies and to the physical mechanisms that can be practically exploited for injecting electrical charge into a floating gate through the isolating dielectric, which often forms the gate dielectric of the complete structure (transistor) of the cell.
Relevant mechanisms will now be described. The so called Fowler-Nordheim (FN) tunnelling mechanism is operative with relatively thin oxide layers and requires a strong electric field. The direct tunnelling mechanism (DT) is operative with relatively thin oxide layers and with a relatively low electric field, is important for the charge retention, and establishes the lower level of the gate oxide scaling in nonvolatile memories. The tunnelling mechanism (IN) is assisted by charge traps in the dielectric created from electrical stresses and which represent the principal mechanism of charge loss in flash cells and in EEPROM cells that have been subjected to numerous programming and erasing cycles. The hot channel carrier injection mechanism is operative throughout an ample range of dielectric thickness and electric field intensities. Of course the above mechanisms, with the exception of the last, may theoretically be exploited also for extracting charge from the floating gate, i.e. for erasing the cell, though the voltage levels must be compatible with the physical-electrical structure of the cell.
It is evident that the charge and discharge mechanism of the floating gate will dictate the structure of the memory cell and of the overhead circuitry, with particular regard to writing, reading and eventually also the erasing circuits of the memory. This imposes case-by-case precise requirements of voltage and current levels necessary for programming and eventually erasing data stored in the memory, besides those required for reading them.
The need of altering the content of the memory by single "words" (herein intended to indicate a unit of information composed of a certain number of bits, for example 8, 16, 32 etc.) without having to reprogram the entire memory as in the case of the so-called EPROM memories, and therefore the requirement of erasing certain selected cells while leaving unchanged the information content of other memory cells, has led to develop the so called EEPROM or E.sup.2 PROM cells, acronyms for Electrically Erasable and Programmable Read Only Memory. Typically, the problem tied to the necessity of biasing the floating gate through its capacitive coupling with a control gate and the semiconducting substrate to charge the floating gate and eventually discharge the electrical charge stored therein, has been satisfied by realizing a capacitive coupling zone between the floating gate and the drain region of the substrate through a thin tunnelling oxide. Through such a tunnelling window the flow of electrons from the isolated gate to the drain region, both during an erasing and a programming phase, occurs by the so-called Fowler-Nordheim tunnelling mechanism, by applying a sufficiently high voltage of one sign or of the opposite sign.
As it is well known, bytewise erasability of EEPROM memories is achieved with a penalty in terms of compactness of the memory cell matrix, these cells being from three to four times larger than an EPROM cell, for the same fabrication technology, because they require the integration of a select transistor associated with each cell. The fabrication process of an EEPROM memory of known kind is notably much more complex than an EPROM process and the EEPROM memory requires relatively more complex overhead circuitry, as well as the integration of voltage multipliers.
The improvement of fabrication technologies has allowed a further reduction of the minimum thickness of the insulating oxide between an insulated gate and the monocrystalline silicon substrate while reliably ensuring a remarkable absence of defects, down to an average thickness of the oxide much smaller than 100 .ANG.. The FLASH cell is programmable through a mechanism of injection of hot channel electrons into the isolated gate, by biasing the gate electrode (control gate) with a sufficiently high positive voltage (for example in the order of 12 V) and the drain with a voltage of about 6V, to produce in the channel region of the cell a strong electric field suitable to generate within the silicon a current of highly energetic (hot) electrons capable of overcoming the potential barrier at the interface with dielectric to be thereafter attracted towards the floating gate by the electric field.
Because of the extreme thinness of the gate dielectric, by applying a relatively high voltage (up to 12V depending on the fabrication technology) to the source while maintaining the other electrodes to ground potential, the electrons injected into the floating gate are able to cross the thin dielectric according to a Fowler-Nordheim tunnelling mechanism and "discharge" in the source region, during an erasing phase of the memory. The possibility of electrically erasing the memory device without removing it from the printed circuit card for exposing it to UV light has solved a most severe problem of EPROM memories. With the overcoming of this problem, all the intrinsic advantages of EPROM memories, such as the extreme compactness, speed and above all their low cost, have opened an extremely vast field of application.
On the other hand, given that normally the flash memories are block-erasable, there is the possibility during the erasing phase some cells, faster than others, that they be over-erased (depleted) and assume a negative threshold voltage. Since the memory cell has no select transistor, the presence of depleted cells causes reading errors. In fact the reading phase takes place by applying a positive voltage to the selected wordline, being all other wordlines grounded and verifying the current absorbed by the selected bitline. A depleted cell provides current even with its wordline grounded making all other cells of the same bit line be read as "1" even if they are programmed as "0". For this reason, the erasing process of FLASH memories is intrinsically critical and is commonly carried out through a succession of erasing bias pulses followed by verification until completing the erasing of all the cells of the memory. This is done while avoiding inadvertently bringing some of the cells to a depletion state.
Upon completing the erasing phase, unlike the EEPROM cells, which being provided with a select transistor the read current of erased cells is not determined as much by the threshold voltage of the cells but by the current that can be provided by the select transistor, individual FLASH-EPROM cells assume a threshold voltage value that is non-uniform and constant, but is within a certain range of variation. In other words, there is a spread of the threshold values of the cells, the breath of which is tied also to parameters of the fabrication process. Such a spread of the threshold values of the cells must be taken into account by the overhead circuitry of the memory.
To obviate this drawback of FLASH-EPROM memories, a particular cell structure has been proposed, wherein each control gate line (wordline) of the memory overlies (it is capacitively coupled) only for a portion of its width on the relative floating gates of the cells of the row, while the other portion forms the gate of as many select transistors, each associated to the structure of a respective cell of the row. In this way, though with a penalty in terms of compactness, a select transistor is associated to each cell, thus making substantially uniform the threshold value of all the cells once the erasing of the memory array is performed. This technique is described in the paper entitled "A 128K Flash-EEPROM using Double Polysilicon Technology" by George Samachisa, Chien-Sheng Su, Yu-Sheng Kao, George Smarandoiu, Ting Wong, Chenming Hu, presented at the IEEE International Solid State Circuits Conference of Feb. 25, 1987.
Notwithstanding the relatively low cost, speed and compactness of FLASH-EPROM memories, there are some particular applications of such memories which also need to associate to a FLASH-EPROM memory an EEPROM memory block (typically of much lower capacity) for storing data to be frequently altered (updated). These requirements generally occur in systems wherein only a small portion of the data stored in a permanent manner is to be frequently updated, while a vast mass of data is destined to remain unvaried in time or to be modified only at relatively long intervals or only in consequence of exceptional events. Situations of this kind are common in the field of automatic control, regulation, self-diagnostic systems that are increasingly employed in the car industry and in similar industries, wherein periodically it is necessary to modify/update data relative to tests, maintenance, modification of the values of certain operation parameters and so forth.
Block-erasable FLASH-EPROM memories have been proposed to meet these market demands. According to one of these techniques, the possibility of block-erasing the memory is obtained by segmenting the source lines (diffusions), realizing a further order of metallization lines to which the different portions or segments of source lines are connected through interconnection ways, and an additional decoder to select the memory blocks to be erased. Such a technique is described in the patent U.S. Pat. No. 5,289,423.
These systems are intrinsically too rigid to meet the different requirements of users in an optimum way, and imply a remarkable complication of the layout of the memory because of the increased number of metallization levels and the realization of a large number of "cross overs" at cross points between lines of the same level. In the majority of cases, the user requirements could be satisfied in an optimum way by realizing an EEPROM memory block of suitable size, in the same chip containing a FLASH-EPROM memory, typically of much larger capacity, thus avoiding the need of employing two distinct memory devices.
It is well known the difficulty of compatibly integrating in the same device a FLASH-EPROM memory and an EEPROM memory because of their structural differences as well as the different requirements in terms of voltage levels and current capabilities of the overhead circuitry. Problems of compatibility are even more marked in the case of single supply fabrication processes and therefore requiring charge pump circuits and voltage multipliers integrated on the memory device for generating the relatively high voltages needed during programming and erasing phases. Even assuming that compatibility problems can be overcome by complicating the fabrication process as needed (by recourse to numerous additional masking steps) and by duplicating or multiplying the circuitry where needed for generating the different voltages needed during write, read and erase phases of the two different memories, the yield of such a complex process, and therefore the cost of the devices, would be discouraging.
Even solutions offering a pseudo-EEPROM performance (device functionality), though substantially realizing a FLASH-EPROM memory, by exploiting software methods based on momentarily shifting the data on a different support, correcting or updating and rewriting them in the previously erased FLASH-EPROM memory, are burdensome in terms of the considerable time that is requested to the system microprocessor.
In the document EP-A-0704851 in the name of the present assignee, an EEPROM memory compatible FLASH-EPROM is described. According to the invention disclosed in the above document, a byte-wise erasable memory (EEPROM) is realized by employing a FLASH-EPROM cell matrix, organized in rows and columns individually selectable (during a programming and reading phase) through a plurality of wordlines and bit lines, according to a normal memory architecture. The mechanisms of programming (writing) and erasing the cells remain those of a normal FLASH-EPROM cell, i.e. the hot electrons injection mechanism from the channel region to the floating gate of the cell which takes place in a zone close to the drain diffusion, in the programming phase, and the Fowler-Nordheim tunnelling mechanism, which takes place in an overlap zone of the floating gate on the source region, in the erasing phase.
Byte-wise erasability of the memory is provided by realizing an auxiliary byte select structure that comprises a byte selection transistor, to a current terminal of which are connected in common the sources of the cells of a row of the matrix that compose a certain byte, and having the other current terminal connected to a respective line of a plurality of source biasing lines individually selectable by the overhead circuitry. All the byte select transistors arranged along the same row of the matrix have their gate driven in common through a respective line of a plurality of select lines in the same number of the wordlines of the memory matrix. Byte erasing takes place by biasing through the byte select transistor connected in series to the sources of the memory cells of the selected byte to be erased, the sources of the cells and the relative wordlines (control gate of all the cells of the row) with a voltage suitable to generate a FN tunnelling current of electrons from the floating gates of the cells to their respective source regions, while splitting the voltage. In practice, a negative voltage is applied to the wordline and has a value insufficient to cause soft-erasing phenomena on the other unselected memory cells of the same wordline, while "complementary" positive voltage is applied to the sources, through the select transistor, i.e. a voltage that is proportionately reduced if compared to the absolute value of the negative tunnelling voltage to be applied to the control gate (multiplied by the capacitive ratio of the floating gate cell structure). During an erasing phase the drain of the cells may be grounded or left floating.
Continuous improvements in fabrication technologies, while enhancing the compactness of FLASH cells, impose a separation of the whole FLASH memory in individually erasable blocks, isolated from each other in separated tubs (so-called triple-well architecture), such that the erasing of a memory block does not cause a loss of data in adjacent blocks. The size of the subdivision blocks (matrix granularity) is established based on the most convenient compromise between: the increment of silicon area requisite due to the realization of the separation structures and the time necessary for erasing operations that must necessarily include a refresh operation of registered data. This evolution towards an ever more compact matrix architecture, but divided in electrically isolated blocks, realized in distinct tubs, allows the exploitation of a tunnelling (FN) mechanism from the floating gate to the channel region of the cells in place of a Fowler-Nordheim (FN) tunnelling mechanism on a suitable overlap zone of the floating gate on the cell source region to erase the FLASH memory cells, because of the possibility of positive biasing the tub hoisting the channel regions of all the cells of a certain FLASH memory block, being the tub electrically isolated from adjacent tubs.
Furthermore, channel erasing implies a relevant reduction of the absorbed current, with obvious advantages, and favors the scaling down of the gate length of the cells because it eliminates the need of a graded source junction. Such a change of the way of erasing by a Fowler-Nordheim tunnelling scheme instead of a source-gate kind according to a channel-gate scheme, makes the technical solution described in the previously cited European Patent application EP-A-0704851 if not inoperative, at least requiring important changes in the fabrication process and the use of additional masks. The changes are for optimizing the performances of two substantially different kinds of memory cells and thus to introduce a certain divergence from the respective fabrication processes.
It is natural that the technological advances of fabrication processes have re-proposed the objective of realizing an EEPROM memory function via hardware in a truly compatible way with a standard fabrication process of a FLASH-EPROM memory device.